scls307b? january 1996 ? revised january 2003 1 post office box 655303 ? dallas, texas 75265 wide operating voltage range of 2 v to 6 v outputs can drive up to 10 lsttl loads low power consumption, 80- a max i cc typical t pd = 12 ns 4-ma output drive at 5 v low input current of 1 a max eight flip-flops with single-rail outputs clock enable latched to avoid false clocking applications include: ? buffer/storage registers ? shift registers ? pattern generators description/ordering information these devices are positive-edge-triggered octal d-type flip-flops with an enable input. the ?hc377 devices are similar to the ?hc273 devices, but feature a latched clock-enable (clken ) input instead of a common clear. information at the data (d) inputs meeting the setup time requirements is transferred to the q outputs on the positive-going edge of the clock (clk) pulse, if clken is low. clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. when clk is at either the high or low level, the d input has no effect at the output. these devices are designed to prevent false clocking by transitions at clken . ordering information t a package ? orderable part number top-side marking pdip ? n tube sn74hc377n sn74hc377n 40 cto85 c soic dw tube sn74hc377dw hc377 ?40 c to 85 c soic ? dw tape and reel sn74hc377dwr hc377 sop ? ns tape and reel SN74HC377NSR hc377 cdip ? j tube snj54hc377j snj54hc377j ?55 c to 125 c cfp ? w tube snj54hc377w snj54hc377w 55 c to 125 c lccc ? fk tube snj54hc377fk snj54hc377fk ? package drawings, standard packing quantities, thermal data, symbolization, and pcb design guidelines are available at www.ti.com/sc/package. 3212019 910111213 4 5 6 7 8 18 17 16 15 14 8d 7d 7q 6q 6d 2d 2q 3q 3d 4d 1d 1q clken 5q 5d v 8q 4q gnd clk sn54hc377 . . . fk package (top view) cc sn54hc377 ...j or w p ackage sn74hc377 ...dw, n, or ns p ackage (top view) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 clken 1q 1d 2d 2q 3q 3d 4d 4q gnd v cc 8q 8d 7d 7q 6q 6d 5d 5q clk copyright ? 2003, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
scls307b ? january 1996 ? revised january 2003 2 post office box 655303 ? dallas, texas 75265 function table (each flip-flop) inputs output clken clk d output q h x x q 0 l hh l ll x l x q 0 logic diagram (positive logic) clken 1 11 3 2 clk 1d 1q c1 1d c1 1d c1 1d c1 1d c1 1d c1 1d c1 1d c1 1d 5 2q 6 3q 9 4q 12 5q 15 6q 16 7q 19 8q 4 2d 7 3d 8 4d 13 5d 14 6d 17 7d 18 8d
scls307b ? january 1996 ? revised january 2003 3 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ? supply voltage range, v cc ? 0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0 or v i > v cc ) (see note 1) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v cc ) (see note 1) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous output current, i o (v o = 0 to v cc ) 25 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current through v cc or gnd 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal impedance, ja (see note 2): dw package 58 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . n package 69 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ns package 60 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. the package thermal impedance is calculated in accordance with jesd 51-7. recommended operating conditions (see note 3) sn54hc377 sn74hc377 unit min nom max min nom max unit v cc supply voltage 2 5 6 2 5 6 v v cc = 2 v 1.5 1.5 v ih high-level input voltage v cc = 4.5 v 3.15 3.15 v v ih high level in ut voltage v cc = 6 v 4.2 4.2 v v cc = 2 v 0.5 0.5 v il low-level input voltage v cc = 4.5 v 1.35 1.35 v v il low level in ut voltage v cc = 6 v 1.8 1.8 v v i input voltage 0 v cc 0 v cc v v o output voltage 0 v cc 0 v cc v v cc = 2 v 1000 1000 ? t/ ? v input transition rise/fall time v cc = 4.5 v 500 500 ns ? t/ ? v in ut transition rise/fall time v cc = 6 v 400 400 ns t a operating free-air temperature ? 55 125 ? 40 85 c note 3: all unused inputs of the device must be held at vcc or gnd to ensure proper device operation. refer to the ti applicatio n report, implications of slow or floating cmos inputs , literature number scba004.
scls307b ? january 1996 ? revised january 2003 4 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v t a = 25 c sn54hc377 sn74hc377 unit parameter test conditions v cc min typ max min max min max unit 2 v 1.9 1.998 1.9 1.9 i oh = ? 20 a 4.5 v 4.4 4.499 4.4 4.4 v oh v i = v ih or v il i oh 20 a 6 v 5.9 5.999 5.9 5.9 v v oh v i v ih or v il i oh = ? 4 ma 4.5 v 3.98 4.3 3.7 3.84 v i oh = ? 5.2 ma 6 v 5.48 5.8 5.2 5.34 2 v 0.002 0.1 0.1 0.1 i ol = 20 a 4.5 v 0.001 0.1 0.1 0.1 v ol v i = v ih or v il i ol 20 a 6 v 0.001 0.1 0.1 0.1 v v ol v i v ih or v il i ol = 4 ma 4.5 v 0.17 0.26 0.4 0.33 v i ol = 5.2 ma 6 v 0.15 0.26 0.4 0.33 i i v i = v cc or 0 6 v 0.1 100 1000 1000 na i cc v i = v cc or 0, i o = 0 6 v 8 160 80 a c i 2 v to 6 v 3 10 10 10 pf timing requirements over recommended operating free-air temperature range (unless otherwise noted) v t a = 25 c sn54hc377 sn74hc377 unit v cc min max min max min max unit 2 v 5 3 4 f clock clock frequency 4.5 v 25 16 20 mhz f clock clock frequency 6 v 29 19 23 mhz 2 v 100 150 125 t w pulse duration, clk high or low 4.5 v 20 30 25 ns t w pulse duration, clk high or low 6 v 17 25 21 ns 2 v 100 150 125 d 4.5 v 20 30 25 t set p time before clk 2 v 100 150 125 ns clken high or low 4.5 v 20 30 25 clken high or low 6 v 17 25 21 2 v 5 5 5 t h hold time after clk clken inactive or active, data 4.5 v 5 5 5 ns h , 6 v 5 5 5
scls307b ? january 1996 ? revised january 2003 5 post office box 655303 ? dallas, texas 75265 switching characteristics over recommended operating free-air temperature range, c l = 50 pf (unless otherwise noted) (see figure 1) parameter from to v t a = 25 c sn54hc377 sn74hc377 unit parameter from (input) to (output) v cc min typ max min max min max unit 2 v 5 11 3 4 f max 4.5 v 25 54 16 20 mhz f max 6 v 29 64 19 23 mhz 2 v 56 160 240 200 t pd clk any 4.5 v 15 32 48 40 ns t d clk any 6 v 12 27 41 34 ns 2 v 38 75 110 95 t t any 4.5 v 8 15 22 19 ns t y 6 v 6 13 19 16 operating characteristics, t a = 25 c parameter test conditions typ unit c pd power dissipation capacitance per flip-flop no load 30 pf
scls307b ? january 1996 ? revised january 2003 6 post office box 655303 ? dallas, texas 75265 parameter measurement information voltage waveforms setup and hold and input rise and fall times voltage waveforms pulse durations t h t su 50% 50% 50% 10% 10% 90% 90% v cc v cc 0 v 0 v t r t f reference input data input 50% high-level pulse 50% v cc 0 v 50% 50% v cc 0 v t w low-level pulse voltage waveforms propagation delay and output transition times 50% 50% 50% 10% 10% 90% 90% v cc v oh v ol 0 v t r t f input in-phase output 50% t plh t phl 50% 50% 10% 10% 90% 90% v oh v ol t r t f t phl t plh out-of-phase output notes: a. c l includes probe and test-fixture capacitance. b. phase relationships between waveforms were chosen arbitrarily. all input pulses are supplied by generators having the followi ng characteristics: prr 1 mhz, z o = 50 ? , t r = 6 ns, t f = 6 ns. c. for clock inputs, f max is measured when the input duty cycle is 50%. d. the outputs are measured one at a time with one input transition per measurement. e. t plh and t phl are the same as t pd . test point from output under test c l = 50 pf (see note a) load circuit figure 1. load circuit and voltage waveforms
mechanical data mlcc006b october 1996 1 post office box 655303 ? dallas, texas 75265 fk (s-cqcc-n**) leadless ceramic chip carrier 4040140 / d 10/96 28 terminal shown b 0.358 (9,09) max (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) a no. of min max 0.358 0.660 0.761 0.458 0.342 (8,69) min (11,23) (16,26) 0.640 0.739 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32) (18,78) ** 20 28 52 44 68 84 0.020 (0,51) terminals 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 12 13 14 15 16 18 17 11 10 8 9 7 5 4 3 2 0.020 (0,51) 0.010 (0,25) 6 1 28 26 27 19 21 b sq a sq 22 23 24 25 20 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. this package can be hermetically sealed with a metal lid. d. the terminals are gold plated. e. falls within jedec ms-004
mpdi002c ? january 1995 ? revised december 20002 1 post office box 655303 ? dallas, texas 75265 n (r-pdip-t**) plastic dual-in-line package bb ac ad 0.325 (8,26) 0.300 (7,62) 0.010 (0,25) nom gauge plane 0.015 (0,38) 0.430 (10,92) max 20 1.060 (26,92) 0.940 (23,88) 18 0.920 0.850 14 0.775 0.745 (19,69) (18,92) 16 0.775 (19,69) (18,92) 0.745 a min dim a max pins ** (23,37) (21,59) seating plane 14/18 pin only 20 pin vendor option 4040049/e 12/2002 9 8 0.070 (1,78) a 0.045 (1,14) 0.020 (0,51) min 16 1 0.015 (0,38) 0.021 (0,53) 0.200 (5,08) max 0.125 (3,18) min 0.240 (6,10) 0.260 (6,60) m 0.010 (0,25) 0.100 (2,54) 16 pins shown ms-100 variation aa c d d d 0.030 (0,76) 0.045 (1,14) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. falls within jedec ms-001, except 18 and 20 pin minimum body lrngth (dim a). d. the 20 pin end lead shoulder width is a vendor option, either half or full width.
mechanical data msoi003e ? january 1995 ? revised september 2001 1 post office box 655303 ? dallas, texas 75265 dw (r-pdso-g**) plastic small-outline package 16 pins shown 0.419 (10,65) 0.400 (10,15) 0.291 (7,39) 0.299 (7,59) 16 0.400 (10,16) a min a max (10,41) 0.410 0.462 (11,73) (11,51) 0.453 18 0.610 (15,49) (15,24) 0.600 24 dim pins ** 4040000/e 08/01 0.104 (2,65) max 0.004 (0,10) 0.012 (0,30) seating plane 0 ? 8 0.016 (0,40) 0.050 (1,27) 16 0.050 (1,27) 1 a 8 9 0.014 (0,35) 0.020 (0,51) 0.010 (0,25) nom gage plane 0.010 (0,25) 28 0.710 (18,03) 0.700 (17,78) (12,70) (12,95) 0.500 20 0.510 0.010 (0,25) 0.004 (0,10) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). d. falls within jedec ms-013
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